Course 056 Power Integrity: Advanced Design and Characterization

Dr. István Novák, Principal Signal and Power Integrity Engineer, Samtec, Boston, USA, is teaching this 5-day course in Advanced Design and Characterization. Power Distribution Network (PDN) design is becoming one of the biggest design challenges today for systems with increasing speed, power dissipation and density. A multitude of supply voltages and signalling levels come with reduced timing and noise margins. The allowed noise on signals and on supply rails decreases and the increasing density and bandwidth of interconnects link the previously independent power-integrity, signal-integrity and Electro-Magnetic Compatibility (EMC) design domains. Eventually, the power distribution design and characterization becomes a corner stone and enabler for good signal integrity and electromagnetic compatibility. Series filtering for sensitive clock sources, PLLs and SerDes rails require new considerations in component selection. This course is devoted to power distribution design, simulation & measurement with a brief overview of signal-integrity & electromagnetic compatibility.
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This course has no planned course dates.

If you are interested in this course, contact us at cei@cei.se

TECHNOLOGY FOCUS

Power Distribution Network (PDN) design is becoming one of the biggest design challenges today for systems with increasing speed, power dissipation and density.

A multitude of supply voltages and signalling levels come with reduced timing and noise margins. The allowed noise on signals and on supply rails decreases and the increasing density and bandwidth of interconnects link the previously independent power-integrity, signal-integrity and Electro-Magnetic Compatibility (EMC) design domains.

Eventually, the power distribution design and characterization becomes a corner stone and enabler for good signal integrity and electromagnetic compatibility. Series filtering for sensitive clock sources, PLLs and SerDes rails require new considerations in component selection.

Instructor

Dr. István Novák

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COURSE CONTENT

This five-day course is devoted entirely to power distribution design, simulation and measurement with the necessary brief overview of signal-integrity and electromagnetic compatibility principles. Detailed signal-integrity design and validation is covered in the companion course 055 Signal Integrity: Advanced High-Speed Design and Characterization.

The course is based on a large number of hardware (HW) and software (SW) illustrations, shown live during the class. The teaching methodology is based on showing and explaining good and bad design choices, pointing out potential mistakes, discussing pros and cons of options and focusing on manufacturability and robust performance without costly over-design. The course is taught with minimal mathematics, focusing on the physical phenomena and a few easy-to-remember basic rules.

The course explains the underlying physical rules for successful power distribution designs and shows how the same principles, which can be used to obtain worst-case eye-diagrams in signalling, can also be used to efficiently calculate the worst-case transient noise on power-distribution networks. The course explains the importance of DC drop analysis on power planes, the importance of taking the DC and AC bias characteristics of bypass capacitors and ferrites/inductors.

In the design process, emphasis is put on the proper impedance profile of the bypass network and how to use the impedance profile to estimate and evaluate the worst-case transient noise of various design methodologies. The class answers (among others) such important questions as what stackup and layout details matter for power distribution, how many and what value of bypass capacitors we need, and where to place bypass capacitors for effective noise suppression.

In characterization, equal time is devoted to simulations and measurements. In simulations, different modelling techniques and tools are shown for simulating components, power planes and vias. In measurements, the possible time-domain and frequency-domain instruments are reviewed and the proper set-ups, connections and calibrations are discussed. Participants will receive several of the tools and simulation files shown in the class.

Book Information

A copy of the book “Power Distribution Design Methodologies” written by Dr. Novák is handed out to all participants of this course.

WHO SHOULD ATTEND

The course is aimed at engineers, scientists and managers facing power integrity integrity challenges in electronics designs for the computer, communications, consumer, medical, defense or automotive industries.

Only basic understanding of electronic circuits is assumed because the course is delivered through practical illustrations and examples and emphasizes the understanding of the underlying physics.

Whether you are already knowledgeable in circuit design or in the theory of power integrity, you will find many useful tidbits and a solid explanation of the power-integrity discipline.

Day 1

Interaction of Power Integrity, Signal Integrity and Electromagnetic Compatibility

  • Waveforms and Spectra of High-speed Signals and Power Noise
  • Interaction of Power Integrity, Signal Integrity and Electromagnetic Compatibility
  • Grounding and Shielding Rules, PCB Construction Rules, Laminate Choices
  • Unified PDN and SI design: Linear Network Analysis, Sources of PDN Noise
  • Impulse and Step Responses, Calculating Worst-case Transient Noise

Exercises and illustrations: Signal Spectra, Capacitor Droop and Inductor Current in DC-DC Converters

Day 2

Power Distribution Components

  • Characteristics and Parasitics of Various Bypass Capacitor and Inductor Types
  • Single Node PDN Design, Impedance Matching
  • DC-DC Converter Properties, Transient Response, Output Impedance, Loop Stability
  • Selection and Placement of DC-DC Converters
  • Designing Filters for Low-current Circuits (SerDes, PLL, Vref)

Exercises and illustrations: Estimating DC-DC Converter Stability, Component Resonances

Day 3

Power Distribution Design Methodologies

  • DC Drop on Planes and Traces, Choosing the Proper Geometry for DC Power Distribution
  • Determining Copper Weight and Trace Width for Supply Feeds
  • High-frequency Bypassing with Power-ground Laminates, Stackup Selection, Thin and Ultra-thin Laminates
  • Split Planes and Signal Routing over Splits
  • The Procedure of PDN Design, Determining Target Impedance, Point-of-Load PDN Designs from Silicon to DC-DC Converter

Exercises and illustrations: Adding Resistive Voltage Drops, How to Reduce PDN Resonances, PCB Stackup Analysis for PDN

Day 4

Component Selection and Placement through Simulations, Multi-Node Design

  • Synthesizing PDN Impedance: Multi-pole, Big-V, DMB Approaches, Stress Distribution, Portability, Sensitivity and Cost Comparison
  • High-frequency PDN Design, Service Radius of Bypass Capacitors vs. Matched Planes, How to Handle Multiple Supply Rails in the PDN Design
  • How to Identify and Eliminate Capacitor-capacitor and Capacitor-plane Antiresonances, The Role and Impact of Package on PDN Performance
  • Lumped Spreadsheet and SPICE PDN Simulations

Exercises and illustrations: Simulation of Bypass Capacitor Service Area, Output Impedance and Gain-Phase Plots of DC-DC Converters

Day 5

Validation of Power Distribution Networks through Measurements

  • Frequency-domain Impedance Measurement Set-ups for Milliohm Values: Two-port Shunt-Through Connections
  • Where to Measure PDN Noise?
  • Why we Should not Measure Noise Across Bypass Capacitors
  • Considerations for Sub-system and Full-system PDN Measurements
  • Time-domain Measurement Challenges: Uncorrelated External Noise, Dynamic-range Limitations
  • How to Select Instruments for PDN Testing 

Examples and illustrations: How to Measure Reliably Very Low Impedance Values

ALL COURSE DATES FOR THE CATEGORY:

EMC, SI, PI.

054 Signal and Power Integrity: Advanced High-Speed Design and Characterization

Location: Barcelona, Spain Date: April 13-17, 2026 Duration: 5 days
Instructor: Dr. István Novák. With machine learning and artificial intelligence needs on the rise, the thousands of amperes currents on some of the power rails create unique challenges across our designs, manufacturing and validation. Properly designed power distribution is a key requirement to achieve good signal integrity and to avoid electro-magnetic interference problems. As companies are working towards data rates over 400 Gbps and main-stream serial signaling is in the 5-10 Gbps range; signal rise and fall times shrink to single digit picoseconds. As a result of these signal and power integrity trends, laminate and copper characteristics, glass-weave effects and surface roughness, frequency-dependent trace and component parameters, inter-symbol interference (ISI), jitter and finite bit-error-rate (BER) all need to be re-evaluated and reconsidered. With the increasing utilization of equalization and pre-emphasis, validations even with eye diagrams may not be sufficient. Today, equally challenging is the proper design of power distribution. A multitude of supply voltages, shrinking target impedance values approaching tens of microohms and higher channel attenuations come with reduced timing and noise margins. The allowed noise on signals and on supply rails decreases and the increasing density and bandwidth of interconnects inter-link the previously independent power-integrity, signal-integrity and EMC design domains. Also, the mere definition of impedance on a power rail with tens of microohms impedance becomes non-trivial. Read full course description including course schedule.

Early Bird
3 540,00 €3 935,00 €
Early Bird Price Ends: February 13, 2026

Go to Register
EMC, SI, PI.

060 Grounding and Shielding: The Essence of EMC Design

Location: Barcelona, Spain Date: April 13-16, 2026 Duration: 4 days
Instructor: Mr. Elya B. Joffe. Modern electronics are extremely vulnerable to electrical transients and overstress, which are “predictably unpredictable”. Protection measures can be designed and implemented, are available, but many businesses are not aware of the threat and/or not willing to invest the time or money: There is a prevailing “It Can’t Happen” attitude. This 4-day course will provide the engineering know-how, to describe transient protection and mitigation techniques and to provide the technical tools enabling the engineer to analyze the vulnerability of equipment and design protection of product, systems and facilities, to transients and electrical overstress in electronic circuits and installations, in order to meet the applicable standards and codes. Read full course description including course schedule.

Early Bird
2 940,00 €3 265,00 €
Early Bird Price Ends: February 13, 2026

Go to Register
EMC, SI, PI.

070 High-Speed PCB Design for EMC and Signal Integrity

Location: Gothenburg, Sweden Date: June 22 - June 26, 2026 Duration: 5 days
Instructor: Mr. Elya B. Joffe. All EMI problems begin and end on the Printed Circuit Board. In recent years, PCBs have become increasingly complex. The use of high density VLSI on the one hand, combined with the increased processing speed and data rates on the other hand, have led to the increased density of the circuits. The use of high speed/high edge rate digital circuits, along with the need for low power consumption, have contributed to higher electromagnetic emissions from circuits, on the one hand, and increased sensitivity of the circuits on the other, leading to Electromagnetic Interference (EMI) problems. A special problem is that of Signal Integrity (SI). For the adequate control of EMI, strict international standards and regulations have been developed worldwide. These standards require the suppression of electromagnetic emissions from circuits and systems, and their increased immunity to externally induced interference. The proper design of PCBs is a cost effective approach for the control of EMI in high-speed circuits. Read full course description including course schedule.

Early Bird
3 540,00 €3 935,00 €
Early Bird Price Ends: April 22, 2026

Go to Register
EMC, SI, PI.

071 Transients and Electrical Overstress Protection in Electronic Systems

Location: Amersfoort, The Netherlands Date: May 18 - May 20, 2026 Duration: 3 days
Instructor: Mr. Elya B. Joffe. Modern electronics are extremely vulnerable to electrical transients and overstress, which are “predictably unpredictable”. Protection measures can be designed and implemented, are available, but many businesses are not aware of the threat and/or not willing to invest the time or money: There is a prevailing “It Can’t Happen” attitude. This 3-day course will provide the engineering know-how, to describe transient protection and mitigation techniques and to provide the technical tools enabling the engineer to analyze the vulnerability of equipment and design protection of product, systems and facilities, to transients and electrical overstress in electronic circuits and installations, in order to meet the applicable standards and codes. Read full course description including course schedule.

Early Bird
2 280,00 €2 535,00 €
Early Bird Price Ends: March 18, 2026

Go to Register

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