Course 053 Mastering Power Integrity with Signal Integrity and EMC Foundations

Dr. István Novák, Principal Signal and Power Integrity Engineer, Samtec, Boston, USA, is teaching this unique 5-day course focuses on Power Integrity, PI with a broad and unified outlook to Signal Integrity, SI and EMC. It shows that not only the underlying physics, but also many design rules are essentially the same across these disciplines and the seemingly contradictory rules are the result of different initial conditions. The course is based on forty years of teaching, research and successful industrial design experience. It shows working and proven design practices and pitfalls to avoid. It will illustrate live HW and SW demonstrations, ranging from a variety of home-made tools to professional commercial HW and SW. This course is a must for system board and package designers, power engineers and their managers as well as for silicon designers who want to understand the application environment of their chips.

Available course dates

This course has no planned course dates.

If you are interested in this course, contact us at cei@cei.se

TECHNOLOGY FOCUS

Power integrity, PI, has emerged as the latest and still growing challenge for electronic designs, as the landscape for the three disciplines Signal Integrity, Power Integrity and Electromagnetic Compatibility has shifted. While signal integrity, SI, and electromagnetic compatibility, EMC, still pose challenges, their disciplines and the possible pitfalls and their solutions have been more widely studied and understood. Power noise, and its impact on SI and EMC, on the other hand, creates daily new challenges and their solutions are still being worked out. Whether it is component characterization or high-speed channel link budgeting, the power integrity tasks can not be successfully solved without taking into account the signal integrity and EMC principles.

This unique course focuses on PI with a broad and unified outlook to SI and EMC. It shows that not only the underlying physics, but also many design rules are essentially the same across these disciplines and the seemingly contradictory rules are the result of different initial conditions.
The course is based on forty years of teaching, research and successful industrial design experience. It shows working and proven design practices and pitfalls to avoid. It will illustrate live HW and SW demonstrations, ranging from a variety of home-made tools to professional commercial HW and SW.
This course is a must for system board and package designers, power engineers and their managers as well as for silicon designers who want to understand the application environment of their chips.

Instructor

Dr. István Novák

COURSE CONTENT

This unique course provides a unified analysis and design approach to the power-integrity, signal-integrity and electromagnetic compatibility disciplines with the main focus on power distribution network design, validation, testing and simulations. It emphasizes the most recent challenges that the digital and mixed analog/digital designers face, with time devoted to signal integrity analysis, design methods, solutions and component selection.
We will deal with the underlying physical rules with minimal mathematics. With interactive software and live hardware and software demo illustrations, the various good and bad design choices are explained and trade-offs are shown for achieving high-performance yet cost-effective designs.
Among others, the course shows why PI requires the impedance, whereas SI requires scattering parameters for their designs and validation processes.

Participants will learn how bit error rate (BER) and jitter depends on power noise, how to analyse and minimize their effects. You will also learn the surprising fact that conductor surface roughness is actually more detrimental for low-frequency power distribution than for high-speed signaling. We also show the counter-intuitive fact that current distribution in conductors is not uniform even at DC, resulting in geometry-dependent extra losses.

The course provides an overview of power distribution design methodologies and shows that worst-case power noise and worst-case high-speed eye closure can be calculated based on the same principles. Cost-effective PCB stackup, material and component choices are discussed together with simulation and measurement solutions for power distribution networks and high-speed signaling. The course also shows how to select, characterize and measure DC-DC converters and power filters.


Participants will receive several of the tools and simulation files shown in the class as well as the book Power Distribution Design Methodologies. There is an option to purchase the book Frequency-Domain Characterization of Power Distribution Networks at a special discount, available only to course participants.

WHO SHOULD ATTEND

The course is aimed at engineers, scientists and managers facing signal integrity integrity challenges in electronics designs for the computer, communications, consumer, medical, defense or automotive industries.

Only basic understanding of electronic circuits is assumed because the course is delivered through practical illustrations and examples and emphasizes the understanding of the underlying physics.

Whether you are already knowledgeable in circuit design or in the theory of signal integrity, you will find many useful tidbits and a solid explanation of the signal-integrity discipline.

This course will mostly discuss power integrity, but with emphasized and specific outlooks to signal integrity and EMC.

A series of dedicated hardware (HW) and software (SW) illustrations and design examples will show and explain the underlying physical phenomena and major design rules of proper design.

Day one
Common Foundation of Power Integrity, Signal Integrity and EMC

  • How signal spectrum is related to PI, SI and EMC requirements?
  • When do you need time or frequency-domain solutions?
  • Commonalities and differences between power planes and signal traces
  • Characteristic impedance, delay, matching and termination solutions and rules
  • Understanding impedance and scattering matrices for PI and SI use
  • Parasitics of RLC components, how to interpret catalogue data and how to create accurate simulation models for power and signal integrity

Examples, live HW and SW demos: Calculation of interconnect parameters, reflection, matching, signal bandwidth and spectra

Day two
Multi-Line, Loaded and Lossy Interconnects

  • Printed circuit board construction rules, laminate selection; how material properties impact PI, SI and EMC
  • The various types of crosstalk in power and signal networks
  • Crosstalk reduction, crosstalk metrics in time and frequency domain
  • Differential Interconnects, effects of imbalance, interpreting and calculating mixed-mode S parameters and mode conversion
  • Effect of electrical loading and discontinuities on power planes and signal traces
  • Designing for multi-rail power distribution and multi-line signal crosstalk, simultaneous switching noise
  • DC drop on planes, DC power distribution, minimizing voltage drop by proper connections

Examples, live HW and SW demos: Effect of capacitive loading on power planes and transmission bandwidth, designing for a specific crosstalk goal

Day Three
System Design

  • When do we need single-point or multi-point grounding?
  • Grounding options in mixed-mode applications
  • Shielding and electromagnetic interference rules and solutions
  • Skin loss, dielectric loss, surface roughness, laminate and copper selection, through holes and blind/buried Vias, bends, stubs
  • Clock distribution, skew, jitter, jitter separation, relation to bit error rate (BER) and power noise
  • Clock sources and drivers, clock PLLs, spread-spectrum Clocking in signaling and power distribution
  • Jitter tolerance and jitter transfer
  • Inter symbol interference in power and signal integrity, Reverse Pulse Technique and Peak Distortion Analysis; linear network solutions of passive interconnects

Examples, live HW and SW demos: Termination and resonances in power planes and Clock networks

Day four
Power Distribution Design Methodologies

  • DC-DC converters, transient response, output impedance, loop stability
  • Lumped PDN Design, the Target Impedance concepts and its proper use
  • Synthesizing PDN impedance: pros and cons of multi-pole, big-V and other design strategies
  • Bypass capacitor selection and placement, service area of capacitors
  • Connecting the charge time-of-flight and target-impedance concepts
  • Multi-node PDN Design
  • Proper design of power filters

Examples, live HW and SW demos: Simulation of bypass capacitor service area, output impedance and gain-phase plots of DC-DC converters

Day five
Signal and Power Integrity Measurements and Modelling

  • Creating simulation models for DC-DC converters, bypass components, high-speed interconnects
  • Simulating vias, planes, bypass capacitors, DC-DC converter stability and output impedance
  • Major challenges and their solutions in power and signal-integrity measurements

Examples, live HW and SW demos: Measuring very low impedances reliably and accurately, filter design and performance

ALL COURSE DATES FOR THE CATEGORY:

EMC, SI, PI.

054 Signal and Power Integrity: Advanced High-Speed Design and Characterization

Location: Barcelona, Spain Date: April 13-17, 2026 Duration: 5 days
Instructor: Dr. István Novák. With machine learning and artificial intelligence needs on the rise, the thousands of amperes currents on some of the power rails create unique challenges across our designs, manufacturing and validation. Properly designed power distribution is a key requirement to achieve good signal integrity and to avoid electro-magnetic interference problems. As companies are working towards data rates over 400 Gbps and main-stream serial signaling is in the 5-10 Gbps range; signal rise and fall times shrink to single digit picoseconds. As a result of these signal and power integrity trends, laminate and copper characteristics, glass-weave effects and surface roughness, frequency-dependent trace and component parameters, inter-symbol interference (ISI), jitter and finite bit-error-rate (BER) all need to be re-evaluated and reconsidered. With the increasing utilization of equalization and pre-emphasis, validations even with eye diagrams may not be sufficient. Today, equally challenging is the proper design of power distribution. A multitude of supply voltages, shrinking target impedance values approaching tens of microohms and higher channel attenuations come with reduced timing and noise margins. The allowed noise on signals and on supply rails decreases and the increasing density and bandwidth of interconnects inter-link the previously independent power-integrity, signal-integrity and EMC design domains. Also, the mere definition of impedance on a power rail with tens of microohms impedance becomes non-trivial. Read full course description including course schedule.

Early Bird
3 540,00 3 935,00 
Early Bird Price Ends: February 13, 2026

EMC, SI, PI.

060 Grounding and Shielding: The Essence of EMC Design

Location: Barcelona, Spain Date: April 13-16, 2026 Duration: 4 days
Instructor: Mr. Elya B. Joffe. Modern electronics are extremely vulnerable to electrical transients and overstress, which are “predictably unpredictable”. Protection measures can be designed and implemented, are available, but many businesses are not aware of the threat and/or not willing to invest the time or money: There is a prevailing “It Can’t Happen” attitude. This 4-day course will provide the engineering know-how, to describe transient protection and mitigation techniques and to provide the technical tools enabling the engineer to analyze the vulnerability of equipment and design protection of product, systems and facilities, to transients and electrical overstress in electronic circuits and installations, in order to meet the applicable standards and codes. Read full course description including course schedule.

Early Bird
2 940,00 3 265,00 
Early Bird Price Ends: February 13, 2026

EMC, SI, PI.

070 High-Speed PCB Design for EMC and Signal Integrity

Location: Gothenburg, Sweden Date: June 22 - June 26, 2026 Duration: 5 days
Instructor: Mr. Elya B. Joffe. All EMI problems begin and end on the Printed Circuit Board. In recent years, PCBs have become increasingly complex. The use of high density VLSI on the one hand, combined with the increased processing speed and data rates on the other hand, have led to the increased density of the circuits. The use of high speed/high edge rate digital circuits, along with the need for low power consumption, have contributed to higher electromagnetic emissions from circuits, on the one hand, and increased sensitivity of the circuits on the other, leading to Electromagnetic Interference (EMI) problems. A special problem is that of Signal Integrity (SI). For the adequate control of EMI, strict international standards and regulations have been developed worldwide. These standards require the suppression of electromagnetic emissions from circuits and systems, and their increased immunity to externally induced interference. The proper design of PCBs is a cost effective approach for the control of EMI in high-speed circuits. Read full course description including course schedule.

Early Bird
3 540,00 3 935,00 
Early Bird Price Ends: April 22, 2026

EMC, SI, PI.

071 Transients and Electrical Overstress Protection in Electronic Systems

Location: Amersfoort, The Netherlands Date: May 18 - May 20, 2026 Duration: 3 days
Instructor: Mr. Elya B. Joffe. Modern electronics are extremely vulnerable to electrical transients and overstress, which are “predictably unpredictable”. Protection measures can be designed and implemented, are available, but many businesses are not aware of the threat and/or not willing to invest the time or money: There is a prevailing “It Can’t Happen” attitude. This 3-day course will provide the engineering know-how, to describe transient protection and mitigation techniques and to provide the technical tools enabling the engineer to analyze the vulnerability of equipment and design protection of product, systems and facilities, to transients and electrical overstress in electronic circuits and installations, in order to meet the applicable standards and codes. Read full course description including course schedule.

Early Bird
2 280,00 2 535,00 
Early Bird Price Ends: March 18, 2026

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