Clock Distribution Networks

• Problem Definition
• What’s Ahead: The technology roadmap
• ASIC/SoC vs. Full-Custom Design Methodologies
• Standard Clock Trees for SoCs and FPGA
• Min-Delay and Max-Delay Problems
• Data Delay Insertion and Delay Line Circuits
• Clock Delay Insertion and Clock Tuning
• Unbalanced Tunable Clock Distribution Networks
• High Performance Clock Trees
• Passive and Active Deskew in Clock Trees
• Local Clock Generation with Tunable Frequencies

Metastability and Synchronization Failures

• Metastability
• Latches and Flip-Flops
• Measuring Metastability
• Probability and MTBF
• Synchronizer Circuits
• Symmetric Booster Synchronizer
• Latency and Settling Time
• Simulating Metastability

Synchronization of Asynchronous Clock Domains

• Control Synchronizers
• Formal Specification Using STG
• Data Validity of Synchronizers
• Push Synchronizers
• Timing Assumptions
• Faster Synchronizers
• Shared Latch Synchronizers
• FIFO Synchronizers
• Reset Synchronization
• Clock Gating and Selection Synchronizers
• Scan Insertion Synchronizer
• Mutual Exclusion and Arbiter

Common Synchronization Errors

• Avoiding Synchronization
• One flop Synchronizers
• Sneaky and Greedy Paths
• Half Protocol
• Async Clear
• Pulse Synchronizers
• Slow-to-Fast Synchronizers
• Metastability Blocker and Filters
• Parallel, Shared Latch, and Conservative
• Synchronizers
• Patented Circuits for Fast Resolution and Pre-Sampling Shaker and Dual Shaker Synchronizers

Verification of Synchronizers

• Identifying Domain Crossings
• Structural Verification
• Sorting the Domain Crossings
• Grouping Synchronizers
• Connecting Bi-Directional Protocols
• Recognizing Synchronizers
• Employing Formal Tools
• Functional Verification
• Data Verification
• Manual Verification

Multi-Synchronous and Periodic Synchronizers

• Mesochronous/Multi-SyncSynchronization
• Delay Variations
• Data Delay Synchronizers
• Conflict Detection
• Clock Delay Synchronizers
• FIFO Synchronizers
• Clock Edge Synchronizers
• Periodic Domains and Predictive Synchronizers

Multi-Synchronous and Asynchronous Long Interconnect

• Definition of Long Interconnects
• Point-to-Point, Buses and Networks on Chip
• Source-Synchronous and Adaptive-Clocked Interconnect
• Data Encoding: Dual rail and 1-of-4
• Four- and Two-Phase Protocols
• Asynchronous Interconnect
• Dual Rail and 1-of-4 Interconnect
• Two-Phase Dual Rail Interconnect
• Fast Serial Interconnect
• Asynchronous and MixedTiming FIFO
• Pipeline Synchronizers
• LDL Synchronizer

Multi-Clock Domain and GALS SoC

• Synchronizer-Based GALS
• Arbitrated and Handshake Stoppable Clocks
• Wrappers and Asynchronous Ports
• GALS Methodologies
• Desynchronization
• Synchronization in Networks on Chips (NoC)

Multiple Voltage Domains

• Definitions, Sources of Multiple Voltages
• Level Shifting and Isolating Gates
• Combining Voltage and Clock Domains
• Floor-Plan and Layout Constraint

Dynamic Voltage and Frequency Scaling

• DVS versus DVFS
• Global versus Multi-Domain Scaling
• Methods of DVFS