OUTLINE OF THE COURSE
Day 1: Advanced 3D packaging technologies
             – Processes and materials, metrology and defect inspection

1. Trends in heterogeneous integration and advanced packaging
   Chiplet architecture and heterogeneous integration is a mega-trend needed for AI-based applications; it is an additional booster for performance and functionality of advanced microelectronic products, e.g. for high-performance computing, and an enabler for less power consumption. Novel technical developments – chiplet architecture, advanced packaging technologies, including hybrid bonding, and the integration of new materials – will be discussed. Roadmaps and market trends for heterogeneous 3D integration and advanced packaging will be shown.
   
   
2. Processes and materials, and their integration
   Chiplet architectures and their components, designed to achieve high functionality, performance and energy efficiency, will be discussed. Solder microbump/through-silicon-via (TSV) and Cu-Cu hybrid bonding integration schemes, including W2W and D2W technologies, will be shown, and the integration of several new materials will be explained. The categorization of metallurgical contact systems will be done based on metal-physical basics (interdiffusion, intermetallic phase formation and growth), and consequences such as Kirkendall voids and volume change will be explained. This knowledge and the consideration of the properties of the materials that form the contact systems help to achieve high manufacturing yield and to mitigate product reliability issues.
   
   
3. Challenges to metrology and defect inspection
   Chiplet architectures and their components, designed to achieve high functionality, performance and energy efficiency, will be discussed. Solder microbump/through-silicon-via (TSV) and Cu-Cu hybrid bonding integration schemes and process flows provide different challenges to metrology, e.g. overlay accuracy, and to defect inspection, e.g. the visualization of voids in TSVs, microcracks in solder joints, as well as particles and resulting delamination in Cu-Cu bonds. The consequences resulting from the continuous scaling down of the feature sizes will be discussed too.
   
   

Day 2: Fault isolation and package failure analysis

1. Specific tasks for 3D-packaged ICs
   Demanding tasks to physical failure analysis in packaged structures result from the fact that opaque defects have to be localized, imaged and analyzed. This task requires both nondestructive techniques for defect localization and imaging, partially at full-wafer tools in the cleanroom, preparation steps such as deprocessing and cross-sectioning, and destructive detailed analysis of the defect in physical failure analysis labs. Specific tasks for solder microbump/TSV and Cu-Cu hybrid bonding integration schemes and process flows will be explained, and practical examples will be shown.
   
   
2. Workflows for fault isolation and root-cause analysis
   Workflows for fault isolation and for a final root-cause analysis cover several steps:
   1) electrical fault isolation (EFI) to verify the failing electrical characteristic,
   2) nondestructive imaging using microscopic techniques to visualize the defect,
   3) destructive physical failure analysis techniques to expose and analyze the defect, 4) interpretation of the data and determination of the root cause of the failure.
   
   Particular focus will be directed on nondestructive imaging techniques for 3D-stacked ICs. Workflows combining several nondestructive techniques such as scanning acoustic microscopy (SAM) and transmission X-ray microscopy (TXM) will be proposed.
   
   
3. Advanced analytical techniques for package failure analysis
   Analytical techniques for package failure analysis are different to conventional failure analysis in wafer fabs. The need of getting 3D information and to visualize buried defects in opaque packages will be demonstrated. In addition to standard failure analysis techniques and tools such as scanning electron microscopy (SEM), transmission electron microscopy (TEM), focused ion beam (FIB) and several diffraction and spectroscopy techniques, nondestructive techniques such as scanning acoustic microscopy (SAM), quantum diamond microscopy (QDM) and transmission X-ray microscopy (TXM) will be explained, and potential and limitations will be discussed.

 Day 3: Kinetics of degradation processes and reliability engineering

• Analytical techniques for in-situ studies

SEM or TEM imaging of cross-sections through interconnect structures, e.g. prepared mechanically, using laser ablation, or using focused ion beam (FIB) tools, visualize metal structures and defects. However, kinetic studies applying nondestructive characterization techniques are needed for the understanding of degradation processes that eventually cause failure. One technique that has been proven to provide insight into reliability-limiting degradation processes – e.g. electromigration or thermomechanical processes such as microcrack growth – is X-ray microscopy. Nano X-ray computed tomography (XCT) and laminography (XCL) reveal 3D information about materials ageing and degradation.

• Thermomechanical issues and stress-related phenomena

New performance and reliability challenges caused by design/geometry, processes and materials of 3D stacked ICs will be explained. Particularly, the compatibility of multiple materials with specific properties has to be considered in advanced packaging. Different thermal and mechanical properties of the components, e.g. Young’s modulus (E) and coefficient of thermal expansion (CTE), cause thermo-mechanical stress in 3D IC stacks. The packaged-induced thermo-mechanical stress increases the risk of failure caused by delamination along Cu/dielectrics interfaces (adhesive failure) or fracture in dielectrics (cohesive failure). The nondestructive 3D visualization of crack pathways in Cu/low-k interconnect stacks will be shown with nano-XCT.

• Stress-enforces degradation kinetics and electrical failures

Electromigration (EM) is a reliability issue for advanced packaging structures and for multilevel on-chip interconnect backend-of-line (BEoL) stacks. Stress-induced effects that enhance the risk to fail for 3D interconnect structures as well as degradation and failure mechanisms connected to 3D stacking of integrated circuits will be explained. The “conventional” degradation processes in BEoL stacks are accelerated by thermomechanical stress, originated from different CTEs of package materials, and time-to-failure is reduced. Electromigration in Cu structures will be explained, including void nucleation, agglomeration, and growth.