Instructor: Dr. István Novák.

With machine learning and artificial intelligence needs on the rise, the thousands of amperes currents on some of the power rails create unique challenges across our designs, manufacturing and validation. Properly designed power distribution is a key requirement to achieve good signal integrity and to avoid electro-magnetic interference problems. As companies are working towards data rates over 400 Gbps and main-stream serial signaling is in the 5-10 Gbps range; signal rise and fall times shrink to single digit picoseconds. As a result of these signal and power integrity trends, laminate and copper characteristics, glass-weave effects and surface roughness, frequency-dependent trace and component parameters, inter-symbol interference (ISI), jitter and finite bit-error-rate (BER) all need to be re-evaluated and reconsidered. With the increasing utilization of equalization and pre-emphasis, validations even with eye diagrams may not be sufficient. Today, equally challenging is the proper design of power distribution. A multitude of supply voltages, shrinking target impedance values approaching tens of microohms and higher channel attenuations come with reduced timing and noise margins. The allowed noise on signals and on supply rails decreases and the increasing density and bandwidth of interconnects inter-link the previously independent power-integrity, signal-integrity and EMC design domains. Also, the mere definition of impedance on a power rail with tens of microohms impedance becomes non-trivial.

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